1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of integrated circuits and semiconductor devices, and, more particularly, to anneal treatment of semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
During the semiconductor manufacturing process, various different anneal treatments are performed on a semiconductor wafer, for example, during or following oxidation, nitridation, silicidation, ion implants, chemical vapor deposition processes, etc., to achieve effective reaction with the interface as well as the bulk of the semiconductor wafer. A hydrogen or deuterium passivation process is also a known practice performed at elevated temperatures, typically at around 400-500° C. Degradation of operating performance of semiconductor devices (for example, CMOS transistor device structures) due to hot carrier effects attributed to hydrogen desorption at an oxide (typically silicon oxide)/semiconductor (typically silicon) interface has been recognized for many years. It has been proposed to subject such devices to hydrogen (H2) or deuterium annealing at a convenient stage of the device forming process, before or subsequent to the formation of contacts and interconnects.
Field effect transistors (FETs) represent semiconductor devices of particular importance. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length. In general, a manufacturing process that uses silica (SiO2) as gate dielectrics of MOSFETs includes metallization followed by an anneal step at about 400-450° C. Anneal processes are, however, also of importance in the manufacturing of high-k/metal gate transistors.
In principle, there are two well-known processing methods for forming a planar or 3D transistor with a high-k/metal gate (HK/MG) structure: (1) the so-called “gate last” or “replacement gate” technique; and (2) the so-called “gate first” technique. In general, using the “gate first” technique involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon and a protective cap layer, for example, silicon nitride. Thereafter, one or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some stage of the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HK/MG gate structure for the device is formed. Particularly, hydrogen and/or deuterium anneal of high-k gate dielectric FETs showed significant performance improvement in charge reduction, dangling bond reduction and increase of transconductance.
In all of the above-mentioned anneal processes, key determining factors for effective reaction include the process temperature, processing time and the concentration of a particular gas or a mixture of gases used for a particular anneal treatment. By increasing the pressure of the process gas, it is possible to reduce both the processing temperature and the process time. By increasing the gas concentration at the same temperature, the process efficiency may be improved. It should be noted that exposure of semiconductor wafers, or more precisely integrated circuits, to excessive heat generally degrades the quality of the integrated circuits, in an irreversible and cumulative way. This is partly caused by the diffusion of various carriers and ions implanted on the wafer. The diffusion rates do increase with temperature. As the technology and device structures approach the nanometer scale, the limited thermal budget requirement demands higher concentration of the processing gas and/or lower treatment temperature. In fact, hydrogen or deuterium high-pressure anneal (at pressures up to some 20 atm, for example) has been proven to provide excellent performance improvement of semiconductor devices.
However, during the high-pressure anneal, large amounts of the processing gas, for example, deuterium, are needed. The need for the processing gas not only significantly increases the overall manufacturing costs but also the processing gases typically are highly reactive, inflammable, toxic or otherwise dangerous, and when these gases are pressurized, the likelihood of leakage of the gas from the pressure vessel or its support subsystems to the atmosphere increases. Hydrogen/deuterium gas, for example, is highly inflammable, and when high concentrations of hydrogen/deuterium are exposed to oxygen in the atmosphere, it can explode.
In view of the situation described above, the present disclosure provides techniques that allow for the high-pressure anneal of semiconductor devices with a significantly reduced amount of processing gas needed as compared to the art.